A High Performance and Low Latency Fpga Implementation of Cordic Algorithm

CORDIC is generally faster than other approaches when a hardware multiplier (e.g., a microcontroller) is not available, or when the number of gates required to implement the functions it supports should be minimized (e.g., in an FPGA). On the other hand, when a hardware multiplier is available (e.g., in a DSP microprocessor), table-lookup methods and power series are generally faster than CORDIC. In recent years, the CORDIC algorithm has been used extensively for various biomedical applications, especially in FPGA implementations. Here we use Unfolded architecture for CORDIC in order to achieve low latency for rotation and various functions such as multiplication, division logarithmic exponential and trigonometric functions. The approach of this architecture provides high performance and low latency field programmable gate array implementation of rotational CORDIC algorithm. CORDIC device is highly suitable for computing many functions with precisely the same hardware, so they are ideal for applications with an emphasis on reduction of cost (e.g. by reducing gate counts in FPGAs) over speed and low clock rate can be utilized to meet low power consumption requirement.